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2010 Microchip Technology Inc.

Preliminary

DS41350E-page 119

PIC18F/LF1XK50

14.2

Capture Mode

In Capture mode, the CCPR1H:CCPR1L register pair

captures the 16-bit value of the TMR1 or TMR3

registers when an event occurs on the corresponding

CCP1 pin. An event is defined as one of the following:

every falling edge

every rising edge

every 4th rising edge

every 16th rising edge

The event is selected by the mode select bits,

CCP1M<3:0> of the CCP1CON register. When a cap-

ture is made, the interrupt request flag bit, CCP1IF, is

set; it must be cleared by software. If another capture

occurs before the value in register CCPR1 is read, the

old captured value is overwritten by the new captured

value.

14.2.1

CCP PIN CONFIGURATION

In Capture mode, the appropriate CCP1 pin should be

configured as an input by setting the corresponding

TRIS direction bit.

14.2.2

TIMER1/TIMER3 MODE SELECTION

The timers that are to be used with the capture feature

(Timer1 and/or Timer3) must be running in Timer mode or

Synchronized Counter mode. In Asynchronous Counter

mode, the capture operation may not work. The timer to

be used with each CCP module is selected in the T3CON

register (see Section 14.1.1 “CCP Module and Timer

Resources”).

14.2.3

SOFTWARE INTERRUPT

When the Capture mode is changed, a false capture

interrupt may be generated. The user should keep the

CCP1IE interrupt enable bit clear to avoid false inter-

rupts. The interrupt flag bit, CCP1IF, should also be

cleared following any such change in operating mode.

14.2.4

CCP PRESCALER

There are four prescaler settings in Capture mode; they

are specified as part of the operating mode selected by

the mode select bits (CCP1M<3:0>). Whenever the

CCP module is turned off or Capture mode is disabled,

the prescaler counter is cleared. This means that any

Reset will clear the prescaler counter.

Switching from one capture prescaler to another may

generate an interrupt. Also, the prescaler counter will

not be cleared; therefore, the first capture may be from

non-zero

prescaler.

Example 14-1

shows

the

recommended method for switching between capture

prescalers. This example also clears the prescaler

counter and will not generate the “false” interrupt.

EXAMPLE 14-1:

CHANGING BETWEEN

CAPTURE PRESCALERS

FIGURE 14-1:

CAPTURE MODE OPERATION BLOCK DIAGRAM

Note:

If the CCP1 pin is configured as an output,

a write to the port can cause a capture

condition.

CLRF

CCP1CON

; Turn CCP module off

MOVLW

NEW_CAPT_PS ; Load WREG with the

; new prescaler mode

; value and CCP ON

MOVWF

CCP1CON

; Load CCP1CON with

; this value

CCPR1H

CCPR1L

TMR1H

TMR1L

Set CCP1IF

TMR3

Enable

Q1:Q4

CCP1CON<3:0>

CCP1 pin

Prescaler

1, 4, 16

and

Edge Detect

TMR1

Enable

T3CCP1

TMR3H

TMR3L

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